Cadence University Program Member

Cadence University Program Member

Catholic University of Pelotas is a member of the Cadence University Program. This allows the use of Cadence software for teaching and research at UCPel.

cadence-logo logo-ucpel
Last Update: July, 2017

Updated by: Edyd Junges (

The Cadence software is used on the following courses:

Undergraduate courses (Digital IC, Verification):

Electronic Engineering:

 – 363004 – Digital Systems I (60 hours course)

– 363006 – Digital Systems II (60 hours course)

– 363012 – VLSI Circuits Design (60 hours course)

Computer Engineering:

– 363004 – Digital Systems I (60 hours course)

– 363006 – Digital Systems II (60 hours course)

– 369049 – Integrated Circuits Design (60 hours course)

– 369047 – Embedded Systems (60 hours course)

Graduate courses (Digital IC, Verification):

MP 20102 – 1716 – Introduction to VLSI Circuits Design

– MP 40103 – 1723 – VLSI Circuits Design to Digital Signal Processing   

– MP 40102 – 1722 – Embedded Software Testing

Current Research Projects (Digital IC, Verification, Custom IC):

– CDO-CMOS: Optimized Digital Circuits to Digital Signal Processing and Video Coding:

The main goal of this project is to investigate power optimization techniques for CMOS circuits described at a high level of abstraction, emphasizing the Digital Signal Processing and  Video Coding areas. For the development of circuits and specific architectures in this project,  the following tasks ate taken into account: i) Development of dedicated architectures for adaptive filtering algorithms; ii) Use of coefficient decomposition technique for DSP architectures optimization; iii) Design and implementation of efficient arithmetic operators with both precise and imprecise computation for DSP architectures and Video Coding.

– Adaptive Filtering Dedicated Architectures Applied to Biological Signal Processing

In Digital Signal Processing (DSP) applications, adaptive filtering is one of the most widely used strategies. In this project, adaptive filter computation, based on least mean Square (LSM) and Normalized Least Mean Square (NLMS) algorithms is addressed, where the main goal is the development of efficient architectures for cancelling harmonic power line interference application.

– Design and Implementation of Efficient Arithmetic Operators Applied to Dedicated DSP and H.264/AVC Video Coding Architectures

The main focus of this project is the development of efficient arithmetic operators to be applied to DSP and Video Coding areas. Particularly, the project aims at using the mentioned arithmetic operators into the blocks of the circuits of those areas, whose the main objective is to investigate what the impact on performance improvement and power consumption  reduction when the arithmetic operators are used in the dedicated architectures.

– Design and Implementation of Dedicated Hardware Architectures for the new High Efficiency Video Coding (HEVC) Standard

The goal of this project is to investigate the design and implementation of dedicated hardware architectures for video encoding and video decoding modules of the new High Efficiency Video Coding (HEVC) standard. The designed architectures are described in hardware description language and implemented into standard cells, aiming low power dissipation with high performance to meet real-time high resolution video encoding and decoding.





Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134